Japanese Patent Application Laid-Open Publication No. 2004-134547 (Patent Document 1) discloses a technique aiming at obtaining a semiconductor device capable of achieving excellent electric properties by improving a low ON resistance and a blocking effect with ion implantation at relatively low energy. More specifically, to achieve this aim, a trench is formed on a source-side surface in a drift region, a p-type gate region and a gate electrode are provided on a bottom portion of the trench, and a source electrode is formed on an entire surface of a unit device via an insulating film. Also, a narrowest portion of a channel is made deeper than one half of a junction in the p-type gate region. In this manner, a width of a drain-side channel can be narrowed even in ion implantation at low energy, so that the blocking effect in the p-type gate region can be increased.